ITA | ENG
PORTALE DELLA DIDATTICA

Ricerca CERCA
  KEYWORD

Keyword: HARDWARE DESIGN

azienda TESI AZIENDA esteroTESI ALL'ESTERO Advanced 3D-ICE Thermal Modelling: Driving Innovation in High-Performance Computing Architecture Design  JAHIER PAGLIARI DANIELE  DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA  ELECTRONIC DESIGN AUTOMATION - EDA  GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
azienda TESI AZIENDA Advanced Security Techniques for a 16x16 Pixel Thermal Sensor with Integrated Microcontroller  JAHIER PAGLIARI DANIELE  DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA  ELECTRONIC DESIGN AUTOMATION - EDA  GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Approximate Computing Benchmarks for Embedded Systems  SAVINO ALESSANDRO  TESTGROUP - TESTGROUP
DMA-based multi-IP environment for the FPGA on SEcube™ board  PRINETTO PAOLO ERNESTO  GR-21 - TESTGROUP - TESTGROUP
esteroTESI ALL'ESTERO Design Space Exploration for Approximate Computing Systems  DI CARLO STEFANO  SAVINO ALESSANDRO  TESTGROUP - TESTGROUP
azienda TESI AZIENDA Design of a SPMI Slave Interface IP for Power Management IC  JAHIER PAGLIARI DANIELE  DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA  ELECTRONIC DESIGN AUTOMATION - EDA  GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Design of a low-cost frost detector electronic system for professional orchards  DEMARCHI DANILO  GARLANDO UMBERTO  VLSILAB (VLSI theory, design and applications)
Design of a modular long-range low-power electronic system for precision agriculture  GARLANDO UMBERTO  VLSILAB (VLSI theory, design and applications)
Design of dedicated hardware for Artificial Intelligence (AI) using an Embedded Scalable Platform (ESP)  CASU MARIO ROBERTO  VLSILAB (VLSI theory, design and applications)
Effective and secure challenge-response protocol for FPGA-based PUFs (Physical Unclonable Functions)  PRINETTO PAOLO ERNESTO  GR-21 - TESTGROUP - TESTGROUP
Energy-efficient implementation of an SDN switch  CASU MARIO ROBERTO  GIACCONE PAOLO  Telecommunication Networks Group
azienda TESI AZIENDA esteroTESI ALL'ESTERO Exploring Machine Learning techniques for Electronic Design Automation of AMS Integrated Circuits  JAHIER PAGLIARI DANIELE  DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA  ELECTRONIC DESIGN AUTOMATION - EDA  GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
azienda TESI AZIENDA esteroTESI ALL'ESTERO Machine Learning-Assisted Run-Time Power and Thermal Estimation in High-Performance Computing Processors  JAHIER PAGLIARI DANIELE  DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA  ELECTRONIC DESIGN AUTOMATION - EDA  GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
azienda TESI AZIENDA esteroTESI ALL'ESTERO PPACT Evaluation of a Vector Functional Unit  JAHIER PAGLIARI DANIELE  DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA  ELECTRONIC DESIGN AUTOMATION - EDA  GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
azienda TESI AZIENDA esteroTESI ALL'ESTERO Pioneering ARM DSU big.LITTLE Cluster Optimization  JAHIER PAGLIARI DANIELE  DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA  ELECTRONIC DESIGN AUTOMATION - EDA  GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA


© Politecnico di Torino
Corso Duca degli Abruzzi, 24 - 10129 Torino, ITALY
Contatti